In the field of microprocessor implementation and development it is common practice to continually advance the capabilities of a microprocessor core by means of improvements to clock speed and/or performance. Clock speed may be improved by advanced silicon process technology where feature sizes on integrated circuits may be made smaller and smaller as implementation techniques improve. However, it is more likely that large improvements in dock speed will need an overhaul of the implementation of the logic of the device. Typically, in a microprocessor this will entail reorganising the processor's instruction pipeline such that an instruction takes more pipeline steps and each step has a shorter period than used on previous implementations of that microprocessor.
However, performance-per-cycle is likely to be somewhat impaired by the re-pipelining as a longer pipeline takes more cycles to complete the same task. To improve performance-per-cycle many advanced techniques may need to be employed such as predicting the outcome of certain operations—in particular predicting the outcome of instruction sequences that control the flow of the program (branches, jumps, calls, return etc.). Generally functions such as arithmetic have slightly lower performance relative to the previous implementations of a microprocessor, but the increase in top clock speed and the improvements in program flow improve the overall software performance more than the longer pipeline reduces it.
A multi-threaded microprocessor of the type discussed above is described in our British Patent No. GB2311882. This comprises a multithreaded processor, which may receive and execute instructions from a plurality of instruction pipelines. Scheduling logic which monitors the status of the various executing pipelines determines which pipeline's instructions should be executed on each clock cycle. Developments of this system improve the scheduling by monitoring more specific attributes of each instruction pipeline, such as time to complete execution, average execution rate for instructions etc.
However, these characteristics are not essential to embodiments of the present invention. One characteristic that is significant for embodiments of the present invention is that there is differentiation between different instruction sets such as Reduced instruction set computer (RISC) and digital signal processor (DSP) instruction sets in a single pipeline.
We have appreciated that it would be desirable to maintain current relative performance while increasing the dock speed limit for a microprocessor. In effect, to improve performance on two counts at once—one count is the clock speed, and the other is instructions per clock cycle.